Selective Microarchitecture-Level Scaling for Energy Savings

Abstract

Scaling the clock frequency and supply voltage during every cache miss has been shown to substantially reduce the energy dissipation of the processor, while incurring a modest performance penalty. However, not all cache misses have the same effect on performance. Modern superscalar processors may idle during some cache misses, but continue to execute other instructions during other cache misses. Slowing the CPU on these latter cache misses saves little energy, while adversely affecting the overall performance. In this paper we present a small, accurate table-based approach to speculatively identify those cache misses that do and do not benefit from scaling. By judiciously slowing down only those memory instructions for which the processor has a large idle time, we are able to capture most of the energy savings while avoiding much of the performance penalty. Our approach achieves an energy savings of 16% on average through frequency scaling, with a performance penalty of only 6%.