A technique for low power testing of VLSI chips

R. Jayagowri, K. Gurumurthy
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引用次数: 4

Abstract

Power consumption of a circuit is more in test mode than normal mode. The increased heat due to excess power dissipation can open up reliability issue due to electro-migration. In extreme conditions excess power consumption might even result in chip burn outs also. In this paper, we propose a scan flip-flop which helps to reduce the power consumption during test mode without affecting the functional mode requirements. The proposed scan flip-flop use the single latch double edge triggered flip-flop to perform the scanning during test by halving of number of cycles in the clock frequency. The proposed design of clock driving circuit for the scan flip-flop helps to use the same flip-flop during the normal mode for the specified clock frequency. This avoids the redesign of the circuit for normal mode while using the high speed proposed scan flip-flop. The usage of the proposed scan flip-flop reduces the silicon area by 30% - 45% and the power dissipation by 25% - 35%.
VLSI芯片的低功耗测试技术
电路在测试模式下的功耗大于正常模式下的功耗。由于过度的功率耗散而增加的热量可以打开由于电迁移的可靠性问题。在极端情况下,过度的功耗甚至可能导致芯片烧坏。在本文中,我们提出了一种扫描触发器,它有助于在不影响功能模式要求的情况下降低测试模式期间的功耗。所提出的扫描触发器采用单锁存双边触发触发器,通过将时钟频率的周期数减半来执行测试期间的扫描。所提出的扫描触发器时钟驱动电路设计有助于在指定时钟频率的正常模式下使用相同的触发器。这避免了在使用高速扫描触发器的同时,为正常模式重新设计电路。所提出的扫描触发器的使用减少了30% - 45%的硅面积和25% - 35%的功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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