Architecture-Aware Graph-Covering Algorithm for Custom Instruction Selection

Abstract

Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance demands of embedded applications. In recent customized processors, hardware in the form of new function units and the corresponding custom instructions are added to a core processor to meet the critical computational demands of a target application. This paper presents a new method for automatic selection of application-specific processor extensions. We demonstrate the effectiveness of this system across a range of application domains. Our investigations show that considering the architectural constraints in the custom instruction selection leads to improvements in the total performance of the application. Simulations based on domain-specific application benchmark suites show that with the proposed technique, up to 10% performance improvement can be achieved over the traditional graph covering method.