A unified VLSI algorithm for a high performance systolic array implementation of type IV DCT/DST

Abstract

An efficient design approach to derive a unified high performance systolic array architecture for prime length type IV DCT and DST is proposed. This approach is based on a unified VLSI algorithm that uses a parallel restructuring of type IV DCT and DST. It uses parallel pseudo-circular correlation structures as basic computational forms. Most of the unified algorithm can be implemented on the same hardware structure leading to a VLSI chip with a very high percentage of the chip area being used by both the transforms. The unified algorithm can be mapped onto a linear systolic array that have a small number of I/O channels and low I/O bandwidth, which can be efficiently implemented into a VLSI chip.