The UltraSPARC T1 Processor: CMT Reliability

Abstract

Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power, cooling and reliability in today's datacenters. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture to deliver high performance and reliability in a low power and thermal envelope. The UltraSPARC T1 processor combines eight 4-threaded 64b cores, a high bandwidth interconnect crossbar, a shared 3MB L2 cache and four double-width DDR2 DRAM interfaces. Implemented in 90nm CMOS technology, the 378mm2 die consumes only 63W at 1.2GHz. Beyond the ability of CMT to optimize throughput performance, this paper highlights the advantages of CMT in the areas of power and thermal control, reliability, RAS, and design robustness, describing key features of the design relevant to each of these topics