Experiences teaching synthesis of FPGAs and testable ASICS

Abstract

Microelectronic system designers are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic devices such as field-programmable gate arrays (FPGAs). This approach places the emphasis on a high-level design which reduces time to market by relying on synthesis software and programmable logic to produce working prototypes rapidly. These prototypes may then be altered as requirements change or convert into high-volume mask gate arrays or other application-specific integrated circuits (ASICs) when the demand is known to be sufficient. These ASICs, however, must be designed to be testable to screen out those with manufacturing defects. Hence, scan logic must be inserted, test vectors generated and fault grading performed to ensure a high level of testability. Experiences encountered from teaching a two-semester graduate sequence on these topics are summarized.