New anti-punchthrough design for buried channel PMOSFET

Abstract

Suppression of short channel effect (SCE) is one of the key technology for deep submicron CMOS. Surface channel (SC) pMOSFET with p polysilicon has been known as a good candidate to improve SCE while BC pMOSFET has poor SCE. However, SC pMOSFET has several disadvantages, for example, process complexity, boron penetration, and low hole mobility. Especially, gate depletion, which degrades drive current, due to insufficient polysilicon doping becomes more severe for thin gate oxide. Therefore the use of BC pMOSFET is profitable if SCE of BC pMOSFET can be sufficiently reduced. In recent, many of technologies have been proposed to suppress SCE in BC pMOSFET. A 0.15 BC pMOSFET with conventional arsenic punchthrough stopper [1], tilt implanted punchthrough stopper [2], and co-implanted punchthrough stopper with arsenic and phosphorous [3] have been reported. In this report, double arsenic punchthrough stopper (DAPS) is proposed to improve SCE in BC pMOSFET and compared with the conventional structure and the tilt implanted punchthrough stopper structure by using arsenic.