Design of 60-GHz amplifiers based on over neutralization and optimized inter-stage matching networks in 65-nm CMOS

Abstract

This paper proposes a 60-GHz two stage low-noise amplifier (LNA) and a three stage power amplifier (PA) designed with over neutralization and optimized inter-stage matching techniques in 65nm CMOS process. Thanks to the gain-boosting from over neutralization techniques and insertion loss reduction with bandwidth extension from proposed inter-stage matching technique based on micro-strip lines and transformers, the LNA achieves a 18dB gain, 7GHz 3-dB bandwidth, 2.1dBm ZW with a noise figure of 4.9dB, while consuming only 20mW from a supply of 1.2V. And the PA features 20dB gain, >8GHz bandwidth, a 10.4dBm Z1dB with 14% PAE and 14dBm Psat. The proposed techniques also help to reduce the die sizes of the LNA and PA are reduced to 1.18*0.51mm2 and 1.17*0.47mm2 as well.