{"title":"Reliability issues for high-k gate dielectrics","authors":"A. Oates","doi":"10.1109/IEDM.2003.1269429","DOIUrl":null,"url":null,"abstract":"High-k gate dielectric materials are likely to be implemented in Si CMOS processes in the near future. Reliability characteristics that closely match, or exceed, those of SiO/sub 2/ will be one of the primary goals of future development work. In this paper we review the status of reliability studies of high-k gate dielectrics. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fixed charge. The reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. Attainment of reliability goals will require elimination of charging effects, which dominate transistor degradation.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269429","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 43
Abstract
High-k gate dielectric materials are likely to be implemented in Si CMOS processes in the near future. Reliability characteristics that closely match, or exceed, those of SiO/sub 2/ will be one of the primary goals of future development work. In this paper we review the status of reliability studies of high-k gate dielectrics. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fixed charge. The reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. Attainment of reliability goals will require elimination of charging effects, which dominate transistor degradation.