FPGA based GPS receiver design considerations

Abstract

A project to build a GPS receiver using an FPGA for base-band processing began in 2004. The new receiver platform uses a commonly available RF front end ASIC to convert the GPS signals to a suitable IF. The digital design for baseband processing is normally a reasonably straight forward task. However, because the received GPS signals are at such low levels this presents some challenges. One of the main considerations is to avoid contamination of the incoming signals with interference that can be generated from the digital electronics when using an FPGA. In this paper we describe the hardware design process with a focus on avoiding interference while still allowing complex FPGA logic to operate alongside sensitive GPS RF signal processing.