Analysis on the error contribution of various leakages to an ultra-low power voltage reference for WSNs

Abstract

The push to make crucial circuits like voltage references to work in ultra-low bias currents magnify previously ignored leakages incurred by further process scaling. These leakage currents, mostly temperature-dependent and already comparable to the bias currents, will add significant error to the output voltage of such voltage references degrading its temperature coefficient (TC). In this paper, the effects of various parasitic leakages due to triple well parasitic diodes, internal and external gate leakages to the behavior of the output voltage is simulated and modeled. Consequently, the minimum bias current for a target error voltage in the 2-transistor voltage reference topology is defined in the presence of various leakage mechanisms, highlighting the difficulty in further reduction of power while achieving a desired error in modern processes.