A Low Power High Density Double Edge Triggered Flip Flop for Low Voltage Systems

Abstract

The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7% and 39.9% in terms of power dissipation, power delay product and total transistor width respectively. At scaled voltages, the power consumption of the proposed design reduces by 34% and hence the design is suitable for low power, low voltage and high density applications.