Preventing the Side-Channel Leakage of Masked AES S-Box

Abstract

Masking of gates is one of the most popular techniques to prevent Differential Power Analysis (DPA) of AES S- Boxes. However due to the presence of glitches in circuits even masked circuits leak side-channel information. Moti- vated by this fact, we proposed a balanced masked multi- plier where the inputs are synchronized either by sequential components or controlled AND logic, that can be a possible solution for preventing DPA attack on masked implementa- tion of AES S-Boxes. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked multiplier against DPA attacks. Keywords: Side Channel Attacks, Masked Multiplier, AES S-box, Differential Power Analysis