Asynchronous adiabatic design of full adder using dual-rail domino logic

Abstract

In this paper, asynchronous adiabatic design of full adder using dual-rail domino logic is proposed. Asynchronous adiabatic logic is an attractive approach of low-power design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this work, a full adder using DRDAAL (Dual-Rail Domino with Asynchronous Adiabatic Logic) is designed and simulated, which exhibits better power-delay product and reliable logical operations. To improve the speed of circuits, dual-rail domino logic is introduced. The power-delay product of the proposed design is compared with the conventional CMOS full adder and the quasi-adiabatic families of full adder designs. Simulation results show better power-delay product characteristics for clock rates ranging from 100MHz to 200MHz.