Formal validation of virtual finite state machines

Abstract

We describe our experiences in introducing a formal validation tool in several projects that are developing software for AT&T's 5ESS telephone switching system. The tool validates networks of communicating processes implemented in the virtual finite state machine (VFSM) notation, using Holzmann's (1991) super-trace algorithm to check for errors in process interaction such as deadlock, livelock, unexpected inputs, message buffer overflow, and unreachable code. The validator has been used by several 5ESS developers to find bugs in their VFSM designs. We discuss the extent to which the validator has been successfully employed in 5ESS software development, and describe our present research efforts to eliminate some of the roadblocks that stand in the way of its more widespread use.