A fault simulation method based on mutated truth table of logic gates

Abstract

A new fault modeling and simulation method based on VLSI is proposed to evaluate the fault coverage in VLSI accurately. Firstly, inject the circuit-level faults into the logic gates by means of simulation and experiments. Built the fault dictionary consisted of MTTs by analyzing the experimental effect of faults on function. Secondly, considering the MTTs and their weights, a testing coverage model is proposed which is applied to the gate-level fault simulation later. At Last, experiments on standard combinational circuits are done ground on the methods above. The results show that, comparing to the traditional stack-at fault model, the proposed method can better reflect the fault coverage capability of given testing sets.