Fine-Grained Link Locking Within Power and Latency Transaction Level Modelling in Wormhole Switching Non-Preemptive Networks On Chip

Abstract

An increasingly time-consuming part of the design flow of on-chip multiprocessors is simulation of the network on chip (NoC) architecture. Cycle-accurate simulation of state-of-the art network-on-chip interconnects can be prohibitively slow for realistic application examples. In this paper, we identify a time-predictable non-preemptive network-on-chip architecture and propose a TLM model with fine-grained locking of links. The model is tested via simulation of two benchmark application scenarios. Results demonstrate that the proposed algorithm can model the latency upon the majority of flows very closely to the cycle-accurate model, while providing more than 97% accurate power consumption modelling even on the worst case links. This is achieved while simulating nearly three orders of magnitude faster compared to a cycle-accurate model of the same interconnect.