Poster Abstract: Cache Persistence Aware Response Time Analysis for Fixed Priority Preemptive Systems

Abstract

Summary form only given. The existing gap between the processor and main memory operating speeds necessitates the use of intermediate cache memories to accelerate the average case access time to instructions and data that must be executed or treated on the processor. However, the introduction of cache memories in modern computing platforms is the cause of big variations in the execution time of each instruction depending on whether the instruction and the data it treats are already loaded in the cache or not. During the worst-case response time (WCRT) analysis, the existing works assume that each job released by the preempting tasks will ask for their worst-case memory demand. This is however pessimistic since there is a high chance that a big portion of the instructions and data associated with the preempting task τj , are still available in the cache when τj releases its next jobs. We call this content persistent cache blocks (PCBs). In this work, we propose a method to accurately bound the memory overhead incurred by a low priority task due to high priority tasks executing during its response time. For this purpose, we first identify the existence of persistent and nonpersistent cache blocks (i.e., PCBs and nPCBs) associated with each task. We then show with an example that due to the existence of PCBs, the memory demand of a task can significantly vary over time. Therefore, accounting for PCBs in the memory demand of the preempting task allows to reduce the pessimism on the total memory demand considered by the WCRT analysis. Finally, we propose a refined WCRT analysis for fixed priority preemptive systems considering (i) the effect of PCBs on the memory demand of the preempting task, and (ii) accounting for the number of PCBs that can be evicted by the preempted tasks between two successive job releases of the preempting tasks.