An Integrated Security System for Bank Lockers Using Gated D-Latch

Abstract

This paper discusses the design of a Bank locker system. Three different versions of a Bank Locker Security (BLS) System is designed and observed the power consumption at different process corners and different supply voltages. The simulations are measured at 27o C temperature. The power consumption is observed at the supply voltage from 600mV to 1. 2V. The power consumption is less with slow-slow (SS) process corner at 66 MHZ and 200 MHz respectively. This BLS is designed using 45nm CMOS technology.