Thermal Aware Placement in 3D ICs

Abstract

Dominance of on-chip power densities has become a critical design constraint in high-performance VLSI design. This is primarily due to increased technology scaling, number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entail the stacking of multiple active (device) layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the thermal placement of standard cells and gate arrays (modules) taking total wire-length as well as TSVs (through silicon via) into consideration. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of the active layers are not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer, (iv) the estimated total interconnect lengths connecting the modules of the different layers are also improved, and (v) the total number of interlayer vias is quite reasonable. Experimental results on randomly generated and standard benchmark instances are encouraging.