Loss Model and Output Impedance Analysis of a 48V-to-1V High Current Point-of-Load Converter

Abstract

Single-stage, high step-down DC-DC converters for high current point-of-load (POL) applications have become a prominent area of research in order to support new 48V bus architectures. Recently, several converter topologies including resonant-based, hybrid switched-capacitor, and other buck variants have been proposed as high efficiency solutions. However, regardless of topology, the dominant loss in low voltage high current POL converters is the conduction loss, which must be carefully analyzed and minimized. In this paper, a detailed loss breakdown and design methodology for high voltage conversion ratio and high current POL converters are explained. The half-bridge current doubler topology is used as a baseline for analysis and verified with an experimental prototype designed around a nominal operating point of 48V-to-1.2V/80A. Total effective DC output resistance (DCR), frequency dependent resistance (ACR), and the remaining switching losses are addressed as well as integration and layout challenges.