Simultaneous Partitioning and Signals Grouping for Time-Division Multiplexing in 2.5D FPGA-Based Systems

Shih-Chun Chen, Richard Sun, Yao-Wen Chang
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引用次数: 12

Abstract

The 2.5D FPGA is a promising technology to accommodate a large design in one FPGA chip, but the limited number of inter-die connections in a 2.5D FPGA may cause routing failures. To resolve the failures, input/output time-division multiplexing is adopted by grouping cross-die signals to go through one routing channel with a timing penalty after netlist partitioning. However, grouping signals after partitioning might lead to a suboptimal solution. Consequently, it is desirable to consider simultaneous partitioning and signal grouping although the optimization objectives of partitioning and grouping are different, and the time complexity of such simultaneous optimization is usually high. In this paper, we propose a simultaneous partitioning and grouping algorithm that can not only integrate the two objectives smoothly, but also reduce the time complexity to linear time per partitioning iteration. Experimental results show that our proposed algorithm outperforms the state-of-the-arts flow in both cross-die signal timing criticality and system-clock periods.
基于2.5D fpga的时分复用系统的同时分块和信号分组
2.5D FPGA是一种很有前途的技术,可以在一个FPGA芯片中容纳大型设计,但是2.5D FPGA中有限数量的内部芯片连接可能会导致路由失败。为了解决这一问题,采用输入/输出时分复用技术,将交叉芯片信号分组后经过一个路由通道,并在网表划分后产生时序损失。但是,在分区之后对信号进行分组可能会导致次优解决方案。因此,尽管分区和分组的优化目标不同,但需要考虑同时分区和信号分组,并且这种同时优化的时间复杂度通常很高。在本文中,我们提出了一种同时划分和分组的算法,该算法不仅可以顺利地将两个目标整合在一起,而且可以将时间复杂度降低到每次划分迭代的线性时间。实验结果表明,我们提出的算法在交叉芯片信号时序临界性和系统时钟周期方面都优于最先进的流。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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