Delay Restraining of Combined Multiple Input Cross Core Router

Abstract

Delay is arguably one of the most vital Quality of Service (QoS) metrics in computer networks since it has many implications for real time multimedia applications. The congestion and queuing delay of Internet core routers is one of the most important fundamental research topics which plays a vital role in determination of the overall end-to-end delay. In previous works, the control algorithm proposed and modelled in the discrete-time domain, by controlling the value of the threshold within the queue buffer to achieve the required delay, is based on a single arrival in one time slot. In this paper, a new traffic model with the ability to capture the multiple arrivals in a single time slot is described and its application for restraining the delay to a pre-defined value within the network core router is developed. The feasibility of the system is examined using both theoretical analysis and simulation. A statistical evaluation is performed to show both efficiency and accuracy of the results acquired throughout the simulation.