On systematic design of universally capacity approaching rate-compatible sequences of LDPC code ensembles over binary-input output-symmetric memoryless channels

H. Saeedi, H. Pishro-Nik, A. Banihashemi
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引用次数: 2

Abstract

Despite tremendous amount of research on the design of Low-Density Parity-Check (LDPC) codes with belief propagation decoding over different types of Binary-Input Output-Symmetric Memoryless (BIOSM) channels, most results on this topic are based on numerical methods and optimization which do not provide much insight into the design process. In particular, systematic design of provably capacity achieving sequences of LDPC code ensembles over the general class of BIOSM channels, has remained a fundamental open problem. For the case of the Binary Erasure channel, explicit construction of capacity achieving sequences have been proposed based on a property called the flatness condition. In this paper, we propose a systematic method to design universally capacity approaching rate-compatible LDPC code ensemble sequences over BIOSM channels. This is achieved by interpreting the flatness condition over the BEC, as a Successive Maximization (SM) principle that is generalized to other BIOSM channels to design a sequence of capacity approaching ensembles called the parent sequence. The SM principle is then applied to each ensemble within the parent sequence, this time to design rate-compatible puncturing schemes. As part of our results, we extend the stability condition which was previously derived for degree-2 variable nodes to other variable node degrees as well as to the case of rate-compatible codes. Consequently, we rigorously prove that using the SM principle, one is able to design universally capacity achieving rate-compatible LDPC code ensemble sequences over the BEC. Unlike the previous results on such schemes over the BEC in the literature, the proposed SM approach is naturally extendable to other BIOSM channels. The performance of the rate-compatible schemes designed based on our systematic method is comparable to those designed by optimization.
二进制输入输出对称无记忆信道上LDPC码集普遍容量接近速率兼容序列的系统设计
尽管在不同类型的二进制输入输出对称无记忆(BIOSM)信道上设计具有信念传播解码的低密度奇偶校验(LDPC)码进行了大量的研究,但该主题的大多数结果都是基于数值方法和优化,没有提供太多的设计过程的见解。特别是,在一般类型的BIOSM信道上实现LDPC码集成序列的可证明容量的系统设计仍然是一个基本的开放问题。对于二进制擦除信道,基于平坦性条件提出了容量实现序列的显式构造。在本文中,我们提出了一种系统的方法来设计在BIOSM信道上普遍容量接近速率兼容的LDPC码集成序列。这是通过将BEC上的平坦度条件解释为连续最大化(SM)原则来实现的,该原则可推广到其他BIOSM通道,以设计称为父序列的容量接近集成序列。然后将SM原理应用于父序列中的每个集成,这一次是为了设计速率兼容的穿刺方案。作为我们的结果的一部分,我们将之前导出的2度变量节点的稳定性条件推广到其他变量节点度以及速率兼容码的情况下。因此,我们严格证明了使用SM原理,可以设计出在BEC上实现速率兼容的LDPC码集成序列的通用容量。与文献中关于BEC的此类方案的先前结果不同,所提出的SM方法自然可扩展到其他BIOSM通道。基于系统方法设计的速率兼容方案的性能与优化方案相当。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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