A 129.5-151.5GHz Fully Differential Power Amplifier in 65nm CMOS

2019 IEEE MTT-S International Wireless Symposium (IWS) Pub Date : 2019-05-01 DOI:10.1109/IEEE-IWS.2019.8803888

G. Su, Cao Wan, Dirong Chen, Xianghong Gao, Lingling Sun

引用次数: 1

Abstract

This paper presents a 129.5-151.5GHz fully differential power amplifier in 65nm CMOS process. The power amplifier constitutes a two-stage neutralized amplifier and an one-stage cascode amplifier. The neutralized amplifier is employed to improve the gain and isolation of the power amplifier, and the cascode structure is mainly used to improve the output power. The post-layout simulation results show that PA realizes a small signal gain of 10.5dB at the frequency of 139GHz, and the 3dB bandwidth of 22GHz, with a saturated output power of 9dBm, and this power amplifier supports modulation of OOK signal with 20Gbps transmission rate.

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129.5-151.5GHz 65nm CMOS全差分功率放大器

提出了一种采用65nm CMOS工艺的129.5 ~ 151.5 ghz全差分功率放大器。该功率放大器由两级中和放大器和一级级级码放大器组成。中和放大器用于提高功率放大器的增益和隔离度，级联结构主要用于提高输出功率。布放后仿真结果表明，该功率放大器在139GHz频率下实现了10.5dB的小信号增益，3dB带宽为22GHz，饱和输出功率为9dBm，支持传输速率为20Gbps的OOK信号调制。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2019 IEEE MTT-S International Wireless Symposium (IWS)

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