Area efficiency of ADC architectures

Abstract

An empirical design optimization approach is explored for A/D-converter area efficiency. The die area consumption of commonly used ADC architectures is surveyed. Based on trends observed in a large set of empirical data, the area normalized to number of effective quantization steps is proposed as a generic measure of area efficiency. It is seen that state-of-the-art absolute area has a strong correlation with resolution and CMOS node, whereas the proposed measure does not. The state-of-the-art envelopes for normalized area vs. speed, resolution and noise-floor are extracted for each analyzed architecture. Empirically derived guidelines for area-optimal architecture selection based on speed-resolution requirements are given.