A requirements analysis of proposed object oriented VHDL abstractions

Abstract

The paper analyzes benefits gained from object oriented extensions to VHDL by providing and examining example VHDL test cases. Both existing VHDL language features and proposed extensions are examined based on what abstraction benefits are gained from a requirements point of view. The paper concentrates specifically on an analysis of some object oriented extensions proposed by the University of Cincinnati while under contract to Wright Laboratory. Conclusions are based on how well such object oriented extensions work with existing VHDL benefits to provide increased capabilities of the language and associated tools.