Reduction of Fault Latency in Sequential Circuits by using Decomposition

Abstract

The paper discusses a novel approach for reduction of fault detection latency in a self-checking sequential circuit. The Authors propose decomposing the finite state machine (FSM) which describes the sequential circuit of interest, thus obtaining a number of component FSMs respectively describing the number of component circuits. Being decomposed to the number of component circuits, the initial circuit becomes able to detect faults much faster since, at each specific moment of time, one of the component circuits (FSMs) is working and all the others are being tested. The paper deals with the following aspects: a) the decomposition procedure; b) evaluation of the proposed approach based on a fault injection simulation; c) estimation of trade-off between the reduction of latency and the required hardware overhead. Results of the study are tested on a number of standard benchmarks.