FPGA Implementation of LMS and N-LMS Processor for Adaptive Array Applications

Abstract

This paper proposed a fixed-point implementation method of LMS (least mean square) and N-LMS (normalized-LMS) processor. In N-LMS, this paper proposes an efficient method using simple bit-shift operation instead of division. The convergence performance in LMS, N-LMS and RLS (recursive least square) adaptive array antenna is compared by implementation with single large scale FPGA (field programmable gate array) on the same developed hardware platform. It was evaluated by using the actual processing time considering the operation clock speed instead of the number of weight updates. The fixed-point operation with optimized word length and bit-shift operation instead of division are expected to provide faster actual FPGA processing time for LMS families compared with RLS in some specific cases