Conductance DLTS analysis of the correlation between power slump and gate lag

Abstract

Effects of reverse gate-drain current stress on the characteristics of GaAs power MESFET's were investigated. In addition to the previously reported power-slump effect, the gate-lag characteristic became worse. Conductance DLTS measurements of the device before and after stress revealed no new types of surface traps. Further investigation showed gate lag was worsened by a decrease in impact ionization which slowed the hole capture rate. This confirms that power slump is caused by electron traps in the passivation, while gate lag is aggravated by increased sensitivity of existing surface traps to the gate potential.