Miniaturized negative group delay circuit using defected microstrip structure and lumped elements

G. Chaudhary, Y. Jeong, Jongsik Lim
{"title":"Miniaturized negative group delay circuit using defected microstrip structure and lumped elements","authors":"G. Chaudhary, Y. Jeong, Jongsik Lim","doi":"10.1109/MWSYM.2013.6697500","DOIUrl":null,"url":null,"abstract":"In this paper, a design of miniaturized negative group delay circuit (NGDC) using U-shaped defected microstrip structure (DMS) and lumped elements is presented. The resonant center frequency and group delay (GD) time are controlled by an external capacitor and resistor connected across the DMS slot. To verify the design concept, a single stage NGDC is designed, fabricated and compared with the circuit simulation. To get wideband bandwidth of GD, two stages NGDC is also demonstrated and the GD of -7 ns with the maximum insertion loss of 34 dB was obtained over 60 MHz bandwidth.","PeriodicalId":128968,"journal":{"name":"2013 IEEE MTT-S International Microwave Symposium Digest (MTT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE MTT-S International Microwave Symposium Digest (MTT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2013.6697500","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

In this paper, a design of miniaturized negative group delay circuit (NGDC) using U-shaped defected microstrip structure (DMS) and lumped elements is presented. The resonant center frequency and group delay (GD) time are controlled by an external capacitor and resistor connected across the DMS slot. To verify the design concept, a single stage NGDC is designed, fabricated and compared with the circuit simulation. To get wideband bandwidth of GD, two stages NGDC is also demonstrated and the GD of -7 ns with the maximum insertion loss of 34 dB was obtained over 60 MHz bandwidth.
采用缺陷微带结构和集总元件的小型化负群延迟电路
提出了一种基于u型缺陷微带结构和集总元件的小型化负群延迟电路的设计方法。谐振中心频率和群延迟(GD)时间由连接在DMS槽上的外部电容和电阻控制。为了验证设计理念,设计、制作了单级NGDC,并与电路仿真进行了比较。为了获得GD的宽带带宽,还演示了两级NGDC,在60 MHz带宽下获得了-7 ns的GD,最大插入损耗为34 dB。
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