An electronic parallel neural CAM for decoding

Abstract

The authors report measurements taken on an electronic neural system configured for content addressable memory (CAM) using a high-capacity architecture. It is shown that Boltzmann and mean-field learning networks can be implemented in a parallel, analog VLSI system. This system was used to perform experiments with mean-field CAM. The hardware settles on a stored codeword in about 10 mu s roughly independent of code length. The capacity is far higher than that of the standard Hopfield architecture.<>