Vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory at 110nm node

Abstract

We present the structural and electrical characteristics of the latest generation of a self-aligned split-gate NOR memory incorporating a vertical floating-gate channel having 4.5F/sup 2/ area on 110 nm half-pitch rules. With enhanced electric fields for erase and programming, the cell achieves erase time < 1 ms and program time < 10 /spl mu/s at 100nA programming current. These results demonstrate continued scalability of the SuperFlash cell for high-density, high-speed applications.