Comparison of Pipelined Asynchronous Circuits Designed for FPGA

Abstract

Asynchronous circuits where circuit components are controlled by local handshake signals are low power consumption due to the absence of global signals. Various pipelined asynchronous circuits have been proposed. However, it has not been addressed which circuit is better when field programmable gate arrays (FPGAs) are used as the target device. In this paper, we design four pipelined asynchronous circuits for a commercial FPGA. We also describe the modeling method and the design flow. In the experiment, we compare them in terms of circuit area, execution time, dynamic power consumption, and energy consumption.