Extraction of floating-gate capacitive parameters in split-gate flash memory cells

Abstract

A new fast and simple method for extraction of capacitive coupling coefficients in a split-gate flash memory cell is described. The method is based on the modulation of cell's erase characteristics by the bias applied to the gates during read and erase operations. The absolute values of the capacitance between the floating gate and other nodes are also extracted using the effect of modulation of cell conductance caused by the transfer of individual electrons to/from the floating gate.