Design and analysis of a multi-layer transformer balun for silicon RF integrated circuits

Abstract

In this paper, we present the design and analysis of an on-chip transformer balun for silicon RFICs. Both the primary and secondary spread over four metal layers along a common symmetric axis to reduce the overall area, maintaining reasonable quality factor. A five port transformer balun circuit model is developed to facilitate the device simulation. A 4:11 transformer balun is fabricated and tested. It is ideal for LNAs to enhance the gain with optimum noise figure.