Performance evaluation of DC-free error-control block codes

Abstract

DC-free error-control block codes integrate dc-free encoding and error-control block encoding. To reduce the effect of error extension introduced by dc-free decoding and to allow for soft decoding of error-control codes, dc-free error-control block codes are decoded at the receiver by applying error-control decoding techniques prior to dc-free decoding. In this paper, we show that in addition to ensuring both dc-free and error-control properties in the encoded symbol sequence, it is possible to use this coding structure to enforce runlength constraints. We also model the dc-constrained channel with a simple RC high-pass filter, and demonstrate that on this channel with additive white Gaussian noise, dc-free error-control block codes result in superior bit error rate performance, particularly when source data logic values are not equiprobable