Design of Error Tolerant Subtractor using Truncation Approximation Technique

Abstract

In this paper, utilization of a potential method for the design of energy-efficient Very Large Scale Integration (VLSI), specifically for error-resistant applications, such as multimedia and signal processing is taken into consideration. Approximate designing of circuits still produces significant, quick results while consuming little energy. An approximate subtractor is proposed based on the approximate computing using truncation technique of certain part of the circuit for simplification. This paper will discuss the approximate error tolerant subtractor (ETS) design method that will be used in applications like image processing which withstand the slight quality loss. This building block is known to achieve better results in the parameters such as power, delay, power delay product (PDP), and transistor count. This can be used as a basic block in dividers that are used in DSP systems which can tolerate certain amount of errors and help in faster processing of various FFT and DFT processes.