ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions

Abstract

An evaluation of electrostatic-discharge (ESD) reliability by changing the source-end layout of 45-V HV pLDMOS devices is investigated in this paper. After testing and systematic analysis, it can be found that a traditional pLDMOS sample is always very weak in ESD issues (It2= 0.107-A). At the same time, if a pLDMOS with a stripe type embedded SCR (p-n-p-arrangement in the drain-end); the corresponding secondary breakdown-current value can be improved about 501.9% as comparing with a pure pLDMOS. Furthermore, when a pLDMOS-SCR possesses the p-n-p-arranged stripe type and source discrete technique, the trigger voltage (Vt1) values of these samples are all about 45-V ~ 47-V. Next, the holding-voltage (Vh) values were slowly increased with the OD-rows number decreased. Also, the secondary breakdown-current (It2) capabilities are upgraded to 3-A ~ 4-A except for S_DIS 3. Eventually, it can be concluded that a discrete distribution in the source region of a pLDMOS-SCR will upgrade the anti-ESD capability effectively as this embedded SCR is p-n-p-arranged in the drain side.