Multi-standard carrier generator with CMOS logic divider

Seonghan Ryu
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引用次数: 5

Abstract

A multi standard carrier generator chain satisfying all requirements of phase noise and frequency range for Quad-band GSM/EDGE and WCDMA standards is presented. It adopts a VCO utilizing bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain. CMOS logic dividers are also adopted in this LO chain to meet the most stringent phase noise specification of GSM. The proposed divider structure also shows very wide tuning range of self oscillation frequency(0.54 to 2.44GHz). The proposed LO chain is implemented in 0.13 µm CMOS technology. The measured tuning range is about 22% (3.25 to 4.05 GHz). The LO chain exhibits a phase noise of −126, −136 and −164dBc/Hz measured respectively at 400KHz, 1MHz and 20MHz offset from 900MHz Carrier.
带有CMOS逻辑分压器的多标准载波发生器
提出了一种满足四频段GSM/EDGE和WCDMA标准对相位噪声和频率范围要求的多标准载波发生器链。采用高质量因数的键合线电感式压控振荡器,采用8位粗调谐电容组实现低压控振荡器增益。本LO链中还采用了CMOS逻辑分频器,以满足GSM最严格的相位噪声规范。所提出的分频器结构也显示出非常宽的自振荡频率调谐范围(0.54至2.44GHz)。该LO链采用0.13µm CMOS技术实现。测量的调谐范围约为22% (3.25 ~ 4.05 GHz)。LO链的相位噪声分别为- 126、- 136和- 164dBc/Hz,测量频率为400KHz、1MHz和20MHz,载波频率为900MHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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