Extended-butterfly fat tree interconnection (EFTI) architecture for network on chip

H. Hossain, M. Akbar, M. Islam
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引用次数: 15

Abstract

System on chip (SoC) design requires efficient communication between heterogeneous resources to meet the high-speed transmission needs. Therefore one of the key factors for the success of ultra-deep submicron technologies will be the capability of integrating different resources like processor core, memory, an FPGA, a custom hardware block or any other semiconductor intellectual property (SIP) block into a single piece of silicon. Non-scalable global wire delays, global synchronization failure, loss of signal integrity issues are the main problems. To address these problems, various interconnect architectures are proposed. Butterfly fat tree (BFT) is one of those. To improve the performance of BFT we introduce extended-butterfly fat tree interconnection (EFTI). Routing algorithm is provided for EFTI and comparative analysis is performed through the simulation result.
片上网络的扩展蝴蝶胖树互连(EFTI)架构
片上系统(SoC)的设计要求异构资源之间的高效通信,以满足高速传输的需求。因此,超深亚微米技术成功的关键因素之一将是将不同资源(如处理器核心、存储器、FPGA、定制硬件块或任何其他半导体知识产权(SIP)块)集成到单个硅片中的能力。不可扩展的全局线路延迟、全局同步失败、信号完整性丢失等问题是主要问题。为了解决这些问题,提出了各种互连架构。蝴蝶肥树(BFT)就是其中之一。为了提高BFT的性能,我们引入了扩展蝶形脂肪树互连(EFTI)。给出了EFTI的路由算法,并通过仿真结果进行了对比分析。
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