A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller

Abstract

In this letter, the influence on an analog-to-digital converter (ADC) of the dielectric relaxation effect of a metal–oxide–metal (MOM) capacitor is described, agreement of a capacitance model with simulations is shown, and a circuit for canceling the dielectric relaxation effect is proposed. When using an MOM capacitor that exhibits dielectric relaxation in an SAR-ADC for an MCU, accuracy is degraded by switching between multiple analog inputs due to the slow charge and discharge components in the capacitors. In this letter a circuit is proposed in which, by applying the same voltage stress on a local DAC at the negative side input of a comparator as on that at the positive one which samples the single-ended input and performs bit decisions, the influence of the dielectric relaxation effect is converted into common mode error and can be canceled by a differential-input comparator. This ADC is fabricated in a 28-nm embedded flash memory process, and in operation at 5 V and 1 MSps achieves an absolute accuracy error of −1.69/1.38 LSB, an INL of −0.50/0.65 LSB, and a DNL of −0.40/0.28 LSB without being affected by dielectric relaxation.