Design of low leakage power SRAM using multithreshold technique

Abstract

CMOS scaling technology has leads to sub-threshold leakage, effects of short channel, leakage of gate dielectric and device to device variations increase leakage additionally. In SoC (System on Chip), SRAM cell is occupied in the area of about 90%. It has been implementing by using FinFET, though leakage becomes the considerable main factor in SRAM. In addition, for deep submicron technologies the double gate FinFET devices are became a best option in technology where implemented in deep submicron. By this consideration, we proposed to implement 6T SRAM cell using double gate FinFET (DG FinFET) with independent gate which controlled independently with gates opposite sides that maintains excelling scalability for SRAM. The proposed device is applied using different techniques for leakage reduction namely gated Vdd and multithreshold voltage techniques to reduce leakage. Therefore, leakage power in the SRAM cell is decreased and provides better performance. The proposed leakage reduction techniques have been simulated using Cadence in 45 nm technology for FinFET SRAM with independent gate.