Low-leakage Full Adder circuit using Current Comparison Based Domino Logic

Abstract

In this paper, a Full Adder is implemented using a Current Comparison Based Domino Logic which has lower leakage and higher noise immunity without dramatic speed degradation. The technique which is utilized in this paper is based on comparison of mirrored current of the pull-up network with its worst case leakage current. The domino circuit technique which is used here decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper to implement fast Full Adder. Thus, this design can be used to build multipliers so that the power consumption and delay are reduced. The leakage current also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. Simulation results of low leakage high speed full adder shows better results in terms of power dissipation compared to other full adders.