Methodology to Generate Approximate Circuits to Reduce Process Induced Degradation in CNFET Based Circuits

Abstract

A systematic methodology is presented to generate approximate circuits with fewer nodes and shorter paths to reduce process induced degradation due to imperfect process in emerging technologies such as CNFET. In a 16-bit CNFET adder example, at PCNTopen =5%, two resulted approximate adders achieve 80.5% and 90.2% circuit-level pass rate with a penalty of 3.3% and 24.0% in relative logic error, respectively, in comparison with 12.5% pass rate for the precision counterpart. The study paves the path to practically utilize such technology for error-resilient applications.