{"title":"High speed divide by 3/4 prescaler using NMOS like latch block","authors":"Harshal Prajapati, Z. Patel","doi":"10.1109/ICEECCOT52851.2021.9707981","DOIUrl":null,"url":null,"abstract":"A new design technique for 3/4 prescaler that improves operating speed and area is presented. The TSPC based 3/4 prescaler, an NMOS like p and n latch block reduces number of transistors and increases the speed of the 3/4 prescaler. The proposed 3/4 prescaler design can increase operation speed by 18% compared to a 3/4 prescaler design [11] with a 1. SV supply in 180nm CMOS technology. The proposed divide by 5/6 prescaler using the proposed 3/4 prescaler achieves 9.61/9.8 GHz operating frequency with a power consumption of 5.63 mW in divide by five mode and 5.42 mW in divide by six mode.","PeriodicalId":324627,"journal":{"name":"2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEECCOT52851.2021.9707981","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A new design technique for 3/4 prescaler that improves operating speed and area is presented. The TSPC based 3/4 prescaler, an NMOS like p and n latch block reduces number of transistors and increases the speed of the 3/4 prescaler. The proposed 3/4 prescaler design can increase operation speed by 18% compared to a 3/4 prescaler design [11] with a 1. SV supply in 180nm CMOS technology. The proposed divide by 5/6 prescaler using the proposed 3/4 prescaler achieves 9.61/9.8 GHz operating frequency with a power consumption of 5.63 mW in divide by five mode and 5.42 mW in divide by six mode.