High speed divide by 3/4 prescaler using NMOS like latch block

Harshal Prajapati, Z. Patel
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引用次数: 0

Abstract

A new design technique for 3/4 prescaler that improves operating speed and area is presented. The TSPC based 3/4 prescaler, an NMOS like p and n latch block reduces number of transistors and increases the speed of the 3/4 prescaler. The proposed 3/4 prescaler design can increase operation speed by 18% compared to a 3/4 prescaler design [11] with a 1. SV supply in 180nm CMOS technology. The proposed divide by 5/6 prescaler using the proposed 3/4 prescaler achieves 9.61/9.8 GHz operating frequency with a power consumption of 5.63 mW in divide by five mode and 5.42 mW in divide by six mode.
高速除3/4预分频器使用NMOS闩锁块
提出了一种新的3/4预分频器设计方法,提高了运算速度和面积。基于TSPC的3/4预分频器,像p和n锁存器一样的NMOS块减少了晶体管的数量并提高了3/4预分频器的速度。与具有1的3/4预分频器设计[11]相比,所提出的3/4预分频器设计可将运算速度提高18%。SV电源采用180nm CMOS技术。采用所提出的3/4预分频器,所提出的除以5/6预分频器实现了9.61/9.8 GHz的工作频率,除以5模式的功耗为5.63 mW,除以6模式的功耗为5.42 mW。
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