Design and Analysis of Various Narrow-Band LNA Topologies

Ahmed O. El Meligy, L. Albasha
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Abstract

The objective of this paper is to design both a source inductor degenerated low noise amplifier (LNA) and a differential LNA that operate at a radio frequency of 2.4 GHz. The circuit parameters of the LNAs and the test benches are identified by considering the 180 nm generic process design kits (GPDK). The LNAs and test bench schematics are then developed on the Cadence Virtuoso Platform before conducting the simulations and analysis. The obtained results indicate that for the source inductor degenerated LNA, which uses MOSFETs with a gate width of $200\ \mu \mathrm{m}$, a maximum gain of 21.4067 dB is achieved while retaining a minimum noise figure (NF) of 0.367 dB. Furthermore, the 1-dB compression point (PldB) and the input third-order inter-modulation product (IIP3) are found to be −8.172 and −0.513 dBm, respectively. On the other hand, for the differential LNA, using MOSFETs with a gate width of $96\ \mu \mathrm{m}$, the maximum attainable gain is found to be 22.8 dB, and the minimum NF is 2.38 dB. Moreover, −16.634 and −6.547 dBm are obtained for the PldB and the IIP3, respectively.
各种窄带LNA拓扑结构的设计与分析
本文的目的是设计一个源电感退化低噪声放大器(LNA)和一个工作在2.4 GHz射频的差分LNA。采用180 nm通用工艺设计套件(GPDK)确定了LNAs和试验台的电路参数。然后在Cadence Virtuoso平台上开发lna和测试台原理图,然后进行模拟和分析。结果表明,采用栅极宽度为$200\ \mu \ maththrm {m}$的mosfet的源电感退化LNA,最大增益为21.4067 dB,同时保持最小噪声系数(NF)为0.367 dB。此外,1 db压缩点(PldB)和输入三阶互调积(IIP3)分别为- 8.172和- 0.513 dBm。另一方面,对于差分LNA,使用栅极宽度为$96\ \mu \mathrm{m}$的mosfet,可获得的最大增益为22.8 dB,最小NF为2.38 dB。PldB和IIP3分别为−16.634和−6.547 dBm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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