A high speed multi-input comparator with clocking-charge based for low-power systems

Abstract

Currently, a comparison function has been widely used for discrete signal processing. In this study, a novel comparison-cell is presented based on clocking concept. The advantages are that the circuit complexity can be largely reduced and the delay time becomes shorter. The prototype cell is designed for 4-bit comparison cell using Spice simulator. As comparisons with CMOS base, the complexity of proposed cell is reduced to one-third, and the circuit delay can be shortened to half. With a regular design, the prototype of 4/spl times/6 comparison circuit is implemented based on 4-bit basic cell. The chip core is about 0.9mm/sup 2/ using UMC 0.5 /spl mu/m process.