Cache analysis for risc in call processing applications

Abstract

To ensure that ample call processing and other telecommunication processing capacity is available for future demand, the DMS computing core has been undergoing a continuous evolution. Since the introduction of the DMS-100 line of digital switching products, the demand for call processing capacity has steadily increased, justifying our selection of a highly evolvable technology base. Three factors account for this change: increasing requirements to support larger numbers of subscriber lines, in creasing feature penetrations, and increasing real-time requirements for complex features. A recent step in this evolution is the introduction of the DMS-SuperNode using high performance MC68OXX microprocessors. We are now incorporating the benefits of Reduced Instruction Set Computing or RISC technology which has the potential to satisfy future demand for call processing and telecommunication process capacity into the DMS computing core. Because of its highly regular architecture, a RISC processor can pipeline instructions very effectively and hence can operate at very high instruction issuing rates. RISC processors use cache, a high speed buffer inserted between the processor and the main memory, to increase the effective memory access speed. To effectively deploy RISC technology in telecommunications, a deep understanding of cache performance is needed. In developing RISC strategy, BKR scientists carried out an extensive cache analysis. This paper describes the analysis and its results.