{"title":"Artificial neural networks for smart detection of digitally modulated signals","authors":"H.J. Bassai, W. Lorek","doi":"10.1109/GLOCOM.1994.512814","DOIUrl":null,"url":null,"abstract":"We present simple and robust implementations of digital microwave radio receivers. The detection circuit is, essentially, an envelope detector followed by an artificial neural network (ANN). The input signals to the ANN are time-delayed versions of the envelope signal of the digitally modulated carrier in the intermediate frequency (IF) range. A trained ANN assigns its actual input signal waveform to the best fitting carrier state. The networks \"winning\" output is latched and triggers the clock-synchronized generation of the corresponding sequence of data bits. As a special case, we describe the architectural design and the performance optimization of a quadrature phase-shift keying (QPSK) receiver.","PeriodicalId":323626,"journal":{"name":"1994 IEEE GLOBECOM. Communications: The Global Bridge","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1994 IEEE GLOBECOM. Communications: The Global Bridge","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLOCOM.1994.512814","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present simple and robust implementations of digital microwave radio receivers. The detection circuit is, essentially, an envelope detector followed by an artificial neural network (ANN). The input signals to the ANN are time-delayed versions of the envelope signal of the digitally modulated carrier in the intermediate frequency (IF) range. A trained ANN assigns its actual input signal waveform to the best fitting carrier state. The networks "winning" output is latched and triggers the clock-synchronized generation of the corresponding sequence of data bits. As a special case, we describe the architectural design and the performance optimization of a quadrature phase-shift keying (QPSK) receiver.